From d0a372c3112b28ff3b1bf03ff4a7a0e5a3cafe8e Mon Sep 17 00:00:00 2001
From: uvok
Date: Tue, 30 Dec 2025 10:21:27 +0100
Subject: linting, use different naming

use _tb.v instead of .tb.v,
to stop verilator from shouting
the module name doesn't
match
---
 par_to_ser_tb.v | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 par_to_ser_tb.v

(limited to 'par_to_ser_tb.v')

diff --git a/par_to_ser_tb.v b/par_to_ser_tb.v
new file mode 100644
index 0000000..edb1f9b
--- /dev/null
+++ b/par_to_ser_tb.v
@@ -0,0 +1,69 @@
+`timescale 1us/1us
+
+module par_to_ser_tb (
+);
+
+logic clk_i;
+logic rst_i;
+logic data_valid_i;
+logic [7:0] dat_i;
+logic dat_o;
+
+par_to_ser uut (
+  .clk_i(clk_i),
+  .rst_i(rst_i),
+  .data_valid_i(data_valid_i),
+  .dat_i(dat_i),
+  .dat_o(dat_o),
+  .dat_valid_o()
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+  filename=`DUMP_FILE_NAME;
+`else
+  filename="par_to_ser.lxt2";
+`endif
+  $dumpfile(filename); $dumpvars();
+  clk_i = 0;
+  rst_i = 1'b1;
+  data_valid_i = 1'b0;
+
+  #1
+  rst_i = 1'b0;
+  #1
+  rst_i = 1'b1;
+end
+
+always #10 clk_i = ~clk_i;
+
+bit sollbit = 1'b0;
+
+initial begin
+  #13
+  @(negedge clk_i);
+
+  for (integer i = 0; i < 255; i++) begin
+    // clock data in
+    dat_i = i;
+    data_valid_i = 1'b1;
+
+    @(negedge clk_i);
+    data_valid_i = 1'b0;
+
+    for (integer j = 0; j < 8; j++) begin
+      sollbit = (i >> j) & 1;
+      assert(dat_o == sollbit)
+      else $error("Expected bit to be %d, but was %d", sollbit, dat_o);
+
+      @(negedge clk_i);
+    end
+
+    repeat(2) @(negedge clk_i);
+  end
+
+  $finish();
+end
+
+endmodule
-- 
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