From 47c26f27b8be4c6c22ed81f701f1b25072bb3341 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 16 Jan 2026 18:22:10 +0100
Subject: (System)Verilog: Be explicit about wire/logic

---
 playground/clkdiv.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'playground/clkdiv.v')

diff --git a/playground/clkdiv.v b/playground/clkdiv.v
index b6f1419..442ff35 100644
--- a/playground/clkdiv.v
+++ b/playground/clkdiv.v
@@ -1,8 +1,8 @@
 `timescale 1us/1us
 
 module clkdiv (
-    input rst_i,
-    input clk,              // clk input
+    input wire rst_i,
+    input wire clk,              // clk input
     output reg o_divclk     // divided output (must be a reg, b/c it needs to keep state)
 );
 
-- 
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