From 47c26f27b8be4c6c22ed81f701f1b25072bb3341 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 16 Jan 2026 18:22:10 +0100
Subject: (System)Verilog: Be explicit about wire/logic

---
 playground/debounce.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'playground/debounce.v')

diff --git a/playground/debounce.v b/playground/debounce.v
index 33dc22e..4c68e2e 100644
--- a/playground/debounce.v
+++ b/playground/debounce.v
@@ -1,9 +1,9 @@
 `timescale 1us/1us
 
 module debounce (
-  input rst_i,
-  input clk_i,
-  input signal_i,
+  input wire rst_i,
+  input wire clk_i,
+  input wire signal_i,
   output reg signal_o
 );
 
-- 
cgit v1.2.3