From 47c26f27b8be4c6c22ed81f701f1b25072bb3341 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 16 Jan 2026 18:22:10 +0100
Subject: (System)Verilog: Be explicit about wire/logic

---
 playground/fizzbuzz.v | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'playground/fizzbuzz.v')

diff --git a/playground/fizzbuzz.v b/playground/fizzbuzz.v
index 0e34c58..d251198 100644
--- a/playground/fizzbuzz.v
+++ b/playground/fizzbuzz.v
@@ -1,11 +1,11 @@
 `timescale 1us/1us
 
 module fizzbuzz (
-  input [7:0] num_i,
-  output [7:0] num_o,
-  output fizz_o,
-  output buzz_o,
-  output fizzbuzz_o
+  input wire [7:0] num_i,
+  output wire [7:0] num_o,
+  output wire fizz_o,
+  output wire buzz_o,
+  output wire fizzbuzz_o
 );
 
 wire is_fizz, is_buzz;
-- 
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