From 47c26f27b8be4c6c22ed81f701f1b25072bb3341 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 16 Jan 2026 18:22:10 +0100
Subject: (System)Verilog: Be explicit about wire/logic

---
 playground/led.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'playground/led.v')

diff --git a/playground/led.v b/playground/led.v
index e4f4281..bf402d2 100644
--- a/playground/led.v
+++ b/playground/led.v
@@ -3,8 +3,8 @@
 `include "clkdiv.v"
 
 module led (
-    input clk,              // clk input
-    input rst_i,              // reset input
+    input wire clk,              // clk input
+    input wire rst_i,              // reset input
     output reg [5:0] led_o    // 6 LEDS pin
 );
 
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