From 6c83fd8730e55de8b1daaac1deb111d3d9bd408e Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 9 Jan 2026 15:18:23 +0100
Subject: move stuff around

---
 playground/my_mem.v | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 playground/my_mem.v

(limited to 'playground/my_mem.v')

diff --git a/playground/my_mem.v b/playground/my_mem.v
new file mode 100644
index 0000000..1153ec7
--- /dev/null
+++ b/playground/my_mem.v
@@ -0,0 +1,49 @@
+`timescale 1us/1us
+
+`ifndef UVOK_MEMORY
+`define UVOK_MEMORY
+
+module my_mem #(
+  parameter DATA_WIDTH = 8,
+  parameter DATA_DEPTH = 1024
+) (
+  input clk_i,
+
+  input write_en_i,
+  input read_en_i,
+
+  input [$clog2(DATA_DEPTH)-1:0] r_read_addr,
+  input [$clog2(DATA_DEPTH)-1:0] r_write_addr,
+
+  input [(DATA_WIDTH-1) : 0] data_i,
+  output reg [(DATA_WIDTH-1) : 0] data_o
+);
+
+reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0] /* verilator public */;
+
+`ifdef DEBUG
+// for debugging simulations, as iverilog
+// does't show r_datastore
+reg [(DATA_WIDTH-1) : 0] r_cur_r_val;
+reg [(DATA_WIDTH-1) : 0] r_cur_w_val;
+`endif
+
+always @(posedge clk_i) begin
+  if (write_en_i) begin
+    r_datastore[r_write_addr] <= data_i;
+`ifdef DEBUG
+    r_cur_w_val <= data_i;
+`endif
+  end
+
+  if (read_en_i) begin
+    data_o <= r_datastore[r_read_addr];
+`ifdef DEBUG
+    r_cur_r_val <= r_datastore[r_read_addr];
+`endif
+  end
+end
+
+endmodule
+
+`endif
-- 
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