From ba14e988328b250db727b50c9d0db6f0aefc37ff Mon Sep 17 00:00:00 2001
From: uvok
Date: Sat, 10 Jan 2026 17:03:33 +0100
Subject: mem: Add async data output

---
 playground/my_mem.v | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

(limited to 'playground/my_mem.v')

diff --git a/playground/my_mem.v b/playground/my_mem.v
index 1153ec7..c38db3a 100644
--- a/playground/my_mem.v
+++ b/playground/my_mem.v
@@ -16,11 +16,25 @@ module my_mem #(
   input [$clog2(DATA_DEPTH)-1:0] r_write_addr,
 
   input [(DATA_WIDTH-1) : 0] data_i,
-  output reg [(DATA_WIDTH-1) : 0] data_o
+  output reg [(DATA_WIDTH-1) : 0] data_o,
+  output [(DATA_WIDTH-1) : 0] async_data_o
 );
 
 reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0] /* verilator public */;
 
+`ifdef VERILATE
+initial begin
+  r_datastore[0] = 'h11;
+  r_datastore[1] = 'h22;
+  r_datastore[2] = 'h33;
+  r_datastore[3] = 'h44;
+  r_datastore[4] = 'h55;
+  r_datastore[5] = 'h66;
+  r_datastore[6] = 'h77;
+  r_datastore[7] = 'h88;
+end
+`endif
+
 `ifdef DEBUG
 // for debugging simulations, as iverilog
 // does't show r_datastore
@@ -44,6 +58,8 @@ always @(posedge clk_i) begin
   end
 end
 
+assign async_data_o = r_datastore[r_read_addr];
+
 endmodule
 
 `endif
-- 
cgit v1.2.3