From 47c26f27b8be4c6c22ed81f701f1b25072bb3341 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 16 Jan 2026 18:22:10 +0100
Subject: (System)Verilog: Be explicit about wire/logic

---
 playground/template.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'playground/template.v')

diff --git a/playground/template.v b/playground/template.v
index e6f5280..2cbe671 100644
--- a/playground/template.v
+++ b/playground/template.v
@@ -1,8 +1,8 @@
 `timescale 1us/1us
 
 module template (
-  input rst_i,
-  input clk_i
+  input wire rst_i,
+  input wire clk_i
 );
 
 always @(posedge clk_i or negedge rst_i) begin
-- 
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