From 40585222bc7c99193a6205a889d9ae00439c2b37 Mon Sep 17 00:00:00 2001
From: uvok
Date: Fri, 26 Dec 2025 18:04:26 +0100
Subject: Add quick-and-dirty serial/parallel converters

---
 ser_to_par.v | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 ser_to_par.v

(limited to 'ser_to_par.v')

diff --git a/ser_to_par.v b/ser_to_par.v
new file mode 100644
index 0000000..754fdc0
--- /dev/null
+++ b/ser_to_par.v
@@ -0,0 +1,23 @@
+// serial to parallel converter
+// Learning:
+// I don't like this.
+// I think I need a signal / way to say "I'm finished"?
+//
+
+module ser_to_par (
+  input rst_i,
+  input clk_i,
+  input dat_i,
+  output reg[7:0] dat_o
+);
+
+always @(posedge clk_i or negedge rst_i) begin
+  if (!rst_i) begin
+    dat_o <= 8'b0;
+  end else begin
+    dat_o[0] <= dat_i;
+    dat_o[7:1] <= dat_o[6:0];
+  end
+end
+
+endmodule
-- 
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