From d0a372c3112b28ff3b1bf03ff4a7a0e5a3cafe8e Mon Sep 17 00:00:00 2001
From: uvok
Date: Tue, 30 Dec 2025 10:21:27 +0100
Subject: linting, use different naming

use _tb.v instead of .tb.v,
to stop verilator from shouting
the module name doesn't
match
---
 ser_to_par_tb.v | 63 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 ser_to_par_tb.v

(limited to 'ser_to_par_tb.v')

diff --git a/ser_to_par_tb.v b/ser_to_par_tb.v
new file mode 100644
index 0000000..e82b56e
--- /dev/null
+++ b/ser_to_par_tb.v
@@ -0,0 +1,63 @@
+`timescale 1us/1us
+
+module ser_to_par_tb (
+);
+
+logic clk_i;
+logic rst_i;
+logic dat_i;
+logic dat_valid;
+logic [7:0] dat_o;
+
+ser_to_par uut (
+  .clk_i(clk_i),
+  .rst_i(rst_i),
+  .dat_i(dat_i),
+  .dat_o(dat_o),
+  .dat_valid_i(dat_valid),
+  .dat_valid_o()
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+  filename=`DUMP_FILE_NAME;
+`else
+  filename="ser_to_par.lxt2";
+`endif
+  $dumpfile(filename); $dumpvars();
+  clk_i = 0;
+  rst_i = 1'b1;
+  dat_i = 1'b1;
+  dat_valid= 1'b0;
+  #1
+  rst_i = 0;
+  #1
+  rst_i = 1;
+end
+
+always #10 clk_i = ~clk_i;
+
+initial begin
+  #13;
+  @(negedge clk_i);
+
+  dat_valid = 1'b1;
+  // start data
+  dat_i = 1'b0;
+  @(negedge clk_i);
+  // - 1 clk cycle, 1 bit later:
+  dat_i = 1'b1;
+
+  repeat (7) @(negedge clk_i);
+  dat_valid = 1'b0;
+
+  // - 7 clk cycle, 7 bits later:
+  assert (dat_o == 8'hfe)
+  else $error("Excected dat_o to be hfe, was h%x", dat_o);
+
+  @(negedge clk_i);
+  $finish();
+end
+
+endmodule
-- 
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