From 54c6b39e460412aa9d888e1728b883aa27ae34bb Mon Sep 17 00:00:00 2001
From: uvok
Date: Tue, 30 Dec 2025 10:06:26 +0100
Subject: tst_delay: Fix testbench name

---
 tst_delay.tb.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tst_delay.tb.v')

diff --git a/tst_delay.tb.v b/tst_delay.tb.v
index 835c93a..41a133a 100644
--- a/tst_delay.tb.v
+++ b/tst_delay.tb.v
@@ -1,7 +1,7 @@
 // try to figure out how iverilog samples edges
 `timescale 1us/1us
 
-module template_tb (
+module tst_delay_tb (
 );
 
 reg clk_i;
-- 
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