From 73eedafc7ebd1b52e960aa6081e6ff8c4d250569 Mon Sep 17 00:00:00 2001 From: uvok Date: Mon, 29 Dec 2025 16:11:01 +0100 Subject: Shut up verilators timescale warnings --- tst_delay.tb.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tst_delay.tb.v') diff --git a/tst_delay.tb.v b/tst_delay.tb.v index d46c8c3..835c93a 100644 --- a/tst_delay.tb.v +++ b/tst_delay.tb.v @@ -1,5 +1,5 @@ // try to figure out how iverilog samples edges -`timescale 1us/1ns +`timescale 1us/1us module template_tb ( ); -- cgit v1.2.3