Learnings:

- Anything that needs to "store" a state must be a reg?
  => wire's can't be assigned in always blocks, yosys complains
- regs must not lead to wires? (unsure where I read that)
- Clock on the tang9k is 27 MHz

Questions:

- Why do so many examples use always @(posedge clk or nededge rst).
  i.e., why is the clk always included?