module clkdiv (
    input rst_i,
    input clk,              // clk input
    output reg o_divclk     // divided output (must be a reg, b/c it needs to keep state)
);

reg [23:0] counter;

always @(posedge clk or negedge rst_i) begin
    if (!rst_i)
        counter <= 24'd0;
//    else if (counter < 24'd1349_9999)       // 0.5s delay
    else if (counter < 24'd674_9999)       // 0.5s delay
        counter <= counter + 1'b1;
    else
        counter <= 24'd0;
end

always @(posedge clk or negedge rst_i) begin
    if (!rst_i)
        o_divclk <= 1'b0;
    else if (counter == 24'd674_9999)       // 0.5s delay
        o_divclk <= ~o_divclk;
    else
        o_divclk <= o_divclk;
end


endmodule