module clkdiv (
    input rst_i,
    input clk,              // clk input
    output reg o_divclk     // divided output (must be a reg, b/c it needs to keep state)
);

reg [23:0] counter;
//  CLK is 27 MHz
//  we want a 2Hz signal at the output
//  and pin needs to *toggle twice* within one period
//  27MHz / 4 = 6750000
localparam DIVISOR = 24'd6_749_999;

always @(posedge clk or negedge rst_i) begin
    if (!rst_i)
        counter <= 24'd0;
    else if (counter < DIVISOR)
        counter <= counter + 1'b1;
    else
        counter <= 24'd0;
end

always @(posedge clk or negedge rst_i) begin
    if (!rst_i)
        o_divclk <= 1'b0;
    else if (counter == DIVISOR)
        o_divclk <= ~o_divclk;
    else
        o_divclk <= o_divclk;
end


endmodule