`timescale 1us/1ns

module debounce_tb (
);

reg rst_i;
reg clk_i;
reg signal_i;
wire signal_o;

integer i = 0;

debounce #(.STABLE_PERIOD(5)) uut(
  .rst_i(rst_i),
  .clk_i(clk_i),
  .signal_i(signal_i),
  .signal_o(signal_o)
);

initial begin
  $dumpfile("debounce.lxt2"); $dumpvars();

  clk_i <= 0;
  rst_i <= 1'b1;
  signal_i <= 1'b1;
  #4
  rst_i <= 1'b0;
  #4
  rst_i <= 1'b1;
end

always #10 clk_i = ~clk_i;

initial begin
  // initial key press
  #25
  signal_i <= ~signal_i;
  assert (signal_o == 1'b1);
  #40
  signal_i <= ~signal_i;
  assert (signal_o == 1'b1);

  // try bouncing

  #50

  for (i=0; i < 20; i = i + 1) begin
    #20
    signal_i <= ~signal_i;
    assert (signal_o == 1'b1);
  end
  #20
  signal_i <= ~signal_i;
  assert (signal_o == 1'b1);
  #200
  assert (signal_o == 1'b0);

  #300
  signal_i <= ~signal_i;

  #200
  assert (signal_o == 1'b1);

  #300
  $finish();
end

endmodule