// represents the Ben Eater 8bit computer

`timescale 1us/1us

module eater_computer;
logic clk_in;

/* verilator public_on */
tri [7:0] bus;
logic A_to_bus, bus_to_A,
      B_to_bus, bus_to_B
;
/* verilator public_off */

eater_register A (
  .clk_i(clk_in),
  .en_store_i(bus_to_A),
  .en_output_i(A_to_bus),
  .data_i(bus),
  .data_o(bus)
);

eater_register B (
  .clk_i(clk_in),
  .en_store_i(bus_to_B),
  .en_output_i(B_to_bus),
  .data_i(bus),
  .data_o(bus)
);

`ifdef VERILATOR
initial begin
  $dumpfile("simpc.vvp");
  $dumpvars();

  A_to_bus = 0;
  B_to_bus = 0;
  bus_to_A = 0;
  bus_to_B = 0;
  clk_in = 0;
end

always #2 clk_in = ~clk_in;

initial begin

  #10
  $finish();
end
`endif

endmodule