// represents the Ben Eater 8bit computer

`timescale 1us/1us

// fucking being including so that VScode extensions find this module
//     (because config'ing the include path alone doesn't help)
// vs fucking actually compiling it and tools complaining about the fucking timescale.
`ifndef COMPILING
`include "../playground/my_mem.v"
`endif

module eater_computer(
  input wire clk_in,
  output wire [7:0] debug_bus
);

/* verilator public_on */
tri [7:0] bus, A_out, B_out, RAM_out;
logic A_to_bus, bus_to_A,
      B_to_bus, bus_to_B,
      INS_to_bus, bus_to_INS,
      RAM_to_bus, bus_to_RAM,
      ALU_to_bus
;

assign bus = RAM_to_bus ? RAM_out : 8'bz;

assign debug_bus = bus;
/* verilator public_off */

eater_register A (
  .clk_in(clk_in),
  .en_store_in(bus_to_A),
  .en_output_in(A_to_bus),
  .data_in(bus),
  .bus_out(bus),
  .always_out(A_out)
  // .data(bus)
);

eater_register B (
  .clk_in(clk_in),
  .en_store_in(bus_to_B),
  .en_output_in(B_to_bus),
  .data_in(bus),
  .bus_out(bus),
  .always_out(B_out)
  // .data(bus)
);

tri [7:0] ins_bus_out;
assign bus[3:0] = ins_bus_out[3:0];

eater_register INS (
  .clk_in(clk_in),
  .en_store_in(bus_to_INS),
  .en_output_in(INS_to_bus),
  .data_in(bus),
  .bus_out(ins_bus_out),
  .always_out()
  // .data(ins_bus_out)
);

tri [7:0] mem_adr_bus_out;
tri [3:0] adr_RAM_in = mem_adr_bus_out[3:0];

eater_register MEM_ADR (
  .clk_in(clk_in),
  .en_store_in(bus_to_INS),
  .en_output_in(INS_to_bus),
  .data_in(bus),
  .bus_out(mem_adr_bus_out),
  .always_out()
  // .data(mem_adr_bus_out)
);

// Eater RAM is sync???
my_mem #(
  .DATA_WIDTH(8),
  .DATA_DEPTH(16)
) RAM (
  .clk_i(clk_in),
  .write_en_i(bus_to_RAM),
  // ???
  .read_en_i(RAM_to_bus),
  .r_read_addr(adr_RAM_in),
  .r_write_addr(adr_RAM_in),
  .data_i(bus),
  .data_o(),
  .async_data_o(RAM_out)
);

eater_alu alu (
  .clk_in(clk_in),
  .en_output_in(ALU_to_bus),
  .A_in(A_out),
  .B_in(B_out),
  .subtract_n_add_in(1'b0),
  .bus_out(bus)
);

endmodule