// represents the Ben Eater 8bit computer

`timescale 1us/1us

module eater_computer(
  input wire clk_in,
  output wire [7:0] debug_bus
);

/* verilator public_on */
tri [7:0] bus,
      A_out,
      B_out,
      RAM_out,
      INS_out
;
tri [3:0] PC_out;

logic A_to_bus, bus_to_A,
      B_to_bus, bus_to_B,
      INS_to_bus, bus_to_INS,
      RAM_to_bus, bus_to_RAM,
      ALU_to_bus,
      PC_to_bus, bus_to_PC, PC_count_en,
      bus_to_MAR
;

assign debug_bus = bus;
/* verilator public_off */

eater_register A (
  .clk_in(clk_in),
  .en_store_in(bus_to_A),
  .en_output_in(A_to_bus),
  .data_in(bus),
  .bus_out(bus),
  .always_out(A_out)
  // .data(bus)
);

eater_register B (
  .clk_in(clk_in),
  .en_store_in(bus_to_B),
  .en_output_in(B_to_bus),
  .data_in(bus),
  .bus_out(bus),
  .always_out(B_out)
  // .data(bus)
);

wire [7:0] INS_out_full;

eater_register INS (
  .clk_in(clk_in),
  .en_store_in(bus_to_INS),
  .en_output_in(INS_to_bus),
  .data_in(bus),
  .bus_out(),
  .always_out(INS_out_full)
  // .data(INS_out)
);

// 4 LSB go from INS to BUS
wire [7:0] INS_to_bus_interm = {4'b0, INS_out_full[3:0]};

zbuffer INS_to_bus_buffer (
    .data_in(INS_to_bus_interm),
    .en_output_in(INS_to_bus),
    .data_out(bus)
);

tri [7:0] MEM_ADR_out;
tri [3:0] RAM_adr_in = MEM_ADR_out[3:0];

eater_register MEM_ADR (
  .clk_in(clk_in),
  .en_store_in(bus_to_MAR),
  .en_output_in(1'b0),
  .data_in(bus),
  .bus_out(),
  .always_out(MEM_ADR_out)
  // .data(mem_adr_bus_out)
);

// Eater RAM is "technically" synchronous, but still enables write on clk&w_en.
// However, "my RAM" *always outputs something*, and that's bad.
my_mem #(
  .DATA_WIDTH(8),
  .DATA_DEPTH(16)
) RAM (
  .clk_i(clk_in),
  .write_en_i(bus_to_RAM),
  // doesn't matter
  .read_en_i(),
  .r_read_addr(RAM_adr_in),
  .r_write_addr(RAM_adr_in),
  .data_i(bus),
  .data_o(),
  .async_data_o(RAM_out)
);

zbuffer ram_to_bus_buffer (
    .data_in(RAM_out),
    .en_output_in(RAM_to_bus),
    .data_out(bus)
);

eater_alu alu (
  .clk_in(clk_in),
  .en_output_in(ALU_to_bus),
  .A_in(A_out),
  .B_in(B_out),
  .subtract_n_add_in(1'b0),
  .bus_out(bus)
);

tri [3:0] PC_in;
assign PC_in = bus[3:0];

wire PC_clk_neg = ~clk_in;
counter #(
  .DATA_WIDTH(4)
) PC (
  .clk_in(PC_clk_neg),
  .X_in(PC_in),
  .st_store_X_in(bus_to_PC),
  .count_enable_in(PC_count_en),
  .counter_out(PC_out)
);

tri[7:0] PC_out_full;
assign PC_out_full = {4'b0, PC_out};

zbuffer PC_to_bus_buffer (
    .data_in(PC_out_full),
    .en_output_in(PC_to_bus),
    .data_out(bus)
);

endmodule