// represents the Ben Eater 8bit computer

`timescale 1us/1us

module eater_computer(
  output [7:0] debug_bus
);
logic clk_in;

/* verilator public_on */
tri [7:0] bus;
logic A_to_bus, bus_to_A,
      B_to_bus, bus_to_B,
      INS_to_bus, bus_to_INS
;

assign debug_bus = bus;
/* verilator public_off */

eater_register A (
  .clk_i(clk_in),
  .en_store_i(bus_to_A),
  .en_output_i(A_to_bus),
  .data_i(bus),
  .data_o(bus)
  // .data(bus)
);

eater_register B (
  .clk_i(clk_in),
  .en_store_i(bus_to_B),
  .en_output_i(B_to_bus),
  .data_i(bus),
  .data_o(bus)
  // .data(bus)
);

tri [7:0] ins_bus_out;
assign bus[3:0] = ins_bus_out[3:0];

eater_register INS (
  .clk_i(clk_in),
  .en_store_i(bus_to_INS),
  .en_output_i(INS_to_bus),
  .data_i(bus),
  .data_o(ins_bus_out)
  // .data(ins_bus_out)
);

`ifdef VERILATOR

logic [7:0] debug_value;
logic debug_enable;

bus_writer debugger (
  .in_value(debug_value),
  .in_write_to_output(debug_enable),
  .out_value(bus)
);

initial begin
  $dumpfile("simpc.vvp");
  $dumpvars();

  A_to_bus = 0;
  B_to_bus = 0;
  INS_to_bus = 0;
  bus_to_A = 0;
  bus_to_B = 0;
  bus_to_INS = 0;
  clk_in = 0;
  debug_enable = 0;
  debug_value = 'z;
end

always #2 clk_in = ~clk_in;

initial begin

  @(negedge clk_in);
  debug_value = 'haa;
  debug_enable = 1;

  bus_to_A = 1;
  @(negedge clk_in);
  bus_to_A = 0;
  debug_value = 'hbb;
  bus_to_B = 1;
  @(negedge clk_in);
  bus_to_B = 0;
  debug_value = 'hcc;
  bus_to_INS = 1;
  @(negedge clk_in);
  debug_enable = 0;
  debug_value = 'z;
  bus_to_INS = 0;
  @(negedge clk_in);
  A_to_bus = 1;
  @(negedge clk_in);
  #10
  $finish();
end
`endif

endmodule