// represents the Ben Eater 8bit computer

`timescale 1us/1us

module eater_computer_tb;

logic clk_in;

eater_computer uut (
  .debug_bus(),
  .clk_in(clk_in)
);

logic [7:0] debug_value;
logic debug_enable;

zbuffer debugger (
  .data_in(debug_value),
  .en_output_in(debug_enable),
  .data_out(uut.bus)
);

initial begin
  $dumpfile("simpc.vvp");
  $dumpvars();

  uut.A_to_bus = 0;
  uut.B_to_bus = 0;
  uut.INS_to_bus = 0;
  uut.ALU_to_bus = 0;
  uut.RAM_to_bus = 0;
  uut.PC_to_bus = 0;
  uut.PC_count_en = 0;

  uut.bus_to_A = 0;
  uut.bus_to_B = 0;
  uut.bus_to_INS = 0;
  uut.bus_to_RAM = 0;
  uut.bus_to_PC = 0;
  uut.bus_to_MAR = 0;
  clk_in = 0;
  debug_enable = 0;
  debug_value = 'z;
end

always #2 clk_in = ~clk_in;

initial begin

  @(negedge clk_in);
  debug_enable = 1;

  @(negedge clk_in);
  debug_value = 'h00;
  uut.bus_to_MAR = 1;

  @(negedge clk_in);
  uut.bus_to_MAR = 0;
  debug_value = 'h04;
  uut.bus_to_PC = 1;

  @(negedge clk_in);
  uut.bus_to_PC = 0;
  debug_value = 'haa;
  uut.bus_to_A = 1;

  @(negedge clk_in);
  uut.bus_to_A = 0;
  debug_value = 'hbb;
  uut.bus_to_B = 1;

  @(negedge clk_in);
  uut.bus_to_B = 0;
  debug_value = 'hcc;
  uut.bus_to_INS = 1;

  @(negedge clk_in);
  uut.bus_to_INS = 0;
  debug_value = 'hdd;
  uut.bus_to_RAM = 1;

  @(negedge clk_in);
  uut.bus_to_RAM = 0;

  @(negedge clk_in);
  debug_enable = 0;
  debug_value = 'z;

  @(negedge clk_in);
  uut.A_to_bus = 1;

  @(negedge clk_in);
  assert (uut.bus == 'haa) 
  else   $error("Expected 0xaa (from REG A), got 0x%02x on bus", uut.bus);
  uut.A_to_bus = 0;
  uut.B_to_bus = 1;

  @(negedge clk_in);
  assert (uut.bus == 'hbb) 
  else   $error("Expected 0xbb (from REG B), got 0x%02x on bus", uut.bus);
  uut.B_to_bus = 0;
  uut.INS_to_bus = 1;

  @(negedge clk_in);
  assert (uut.bus == 'h0c) 
  else   $error("Expected 0x0c (from INS), got 0x%02x on bus", uut.bus);
  // ERROR: TODO: should I expect 'zc or '0c ?
  uut.INS_to_bus = 0;

  @(negedge clk_in);
  uut.ALU_to_bus = 1;

  @(negedge clk_in);
  assert (uut.bus == 8'('haa + 'hbb))
  else   $error("Expected 0x%02x (from ALU), got 0x%02x on bus", 8'('haa + 'hbb), uut.bus);
  uut.ALU_to_bus = 0;
  uut.PC_to_bus = 1;

  @(negedge clk_in);
  assert (uut.bus == 'h04) 
  else   $error("Expected 0x04 (from PC), got 0x%02x on bus", uut.bus);
  uut.PC_to_bus = 0;
  uut.RAM_to_bus = 1;

  @(negedge clk_in);
  assert (uut.bus == 'hdd) 
  else   $error("Expected 0xdd (from RAM), got 0x%02x on bus", uut.bus);
  uut.RAM_to_bus = 0;

  @(negedge clk_in);
  debug_enable = 1;
  debug_value = 'h01;
  uut.bus_to_MAR = 1;

  @(negedge clk_in);
  debug_enable = 0;
  debug_value = 'bz;
  uut.bus_to_MAR = 0;
  uut.RAM_to_bus = 1;

  @(negedge clk_in);
  $info("Got 0x%02x from RAM", uut.bus);
  assert (uut.bus !== 'hdd) 
  else   $error("Did NOT expectd 0xdd (from RAM)");

  #10
  $finish();
end

endmodule