`timescale 1us/1us

`ifndef EATER_REGISTER
`define EATER_REGISTER

module eater_register #(
  parameter DATA_WIDTH = 8
) (
  input clk_i,

  // sync? async?
  input en_store_i,
  input en_output_i,

  input [(DATA_WIDTH-1) : 0] data_i,
  output [(DATA_WIDTH-1) : 0] data_o
);

reg [(DATA_WIDTH-1) : 0] r_datastore /* verilator public */;

reg int_output_data;

always @(posedge clk_i) begin
  if (en_store_i) begin
    r_datastore <= data_i;
  end

  int_output_data <= en_output_i;
end

assign data_o = int_output_data ? r_datastore : 'z;

endmodule

`endif