// internal types for eater CPU `ifndef EATER_TYPES `define EATER_TYPES // CPU state (for control flags) typedef enum logic[7:0] { // "regular" states INIT, PC_to_MAR, MEM_to_INS_PC_inc, // Note: // The Ben Eater CPU combines these steps. However. // I got probably a bug in my state machine, // or clock in the data differently, // but if I combine the steps, I'm trying to get // the instruction-dependent next state before // the INS is actually loaded. whoops. // One day later: Possible if we run the decoder on the negedge // PC_inc, // instruction dependent states // LDA: a) LSB of INStruction into MAR LDA_INS_to_MAR, // LDA: b) MEM -> A LDA_MEM_to_A, // ADD: a) LSB of INStruction into MAR ADD_INS_to_MAR, // ADD: b) MEM -> B ADD_MEM_to_B, // ADD: c) ALU -> A ADD_ALU_to_A, // SUB: a) LSB of INStruction into MAR SUB_INS_to_MAR, // SUB: b) MEM -> B SUB_MEM_to_B, // SUB: c) ALU -> A SUB_ALU_to_A, // STA: a) LSB of INStruction into MAR STA_INS_to_MAR, // STA: b) A -> MEM STA_A_to_MEM, // LDI: a) LSB of INStruction into A LDI_INS_to_A, // JMP: a) Put 4 LSB of INS -> PC JMP_INS_to_PC, // JMP: b) Needed??? Wait for value to be clocked in to be actually used // probably not needed JMP_NOP, // OUT: A -> OUT OUT_A_to_OUT, // HALT: set halt flag HALT_st } CpuState; typedef enum logic[3:0] { NOP = 'b0000, LDA = 'b0001, ADD = 'b0010, SUB = 'b0011, STA = 'b0100, LDI = 'b0101, JMP = 'b0110, OUT = 'b1110, HALT_op = 'b1111 } eater_instruction; // CPU control flags `ifdef IVERILOG typedef struct packed { logic A_out, A_in; logic B_out, B_in; logic INS_out, INS_in; logic MAR_in; logic RAM_out, RAM_in; logic ALU_out; logic PC_out, PC_in, PC_count; logic OUT_in; logic halt; } CpuControlFlags; `else typedef struct { logic A_out, A_in; logic B_out, B_in; logic INS_out, INS_in; logic MAR_in; logic RAM_out, RAM_in; logic ALU_out, ALU_subtract_nadd; logic PC_out, PC_in, PC_count; logic OUT_in; logic halt; } CpuControlFlags; `endif `endif