module fifo #(
  parameter DATA_WIDTH = 8,
  parameter DATA_DEPTH = 1024
) (
  input rst_i,
  input clk_i,

  input data_write_i,
  input data_read_i,

  output empty_o,
  output full_o,

  output data_valid_o,

  input [(DATA_WIDTH-1) : 0] data_i,
  output [(DATA_WIDTH-1) : 0] data_o

);

always @(posedge clk_i or negedge rst_i) begin
  if (!rst_i) begin
    
  end
end

endmodule