`timescale 1us/1us

module fifo #(
  parameter DATA_WIDTH = 8,
  parameter DATA_DEPTH = 1024
) (
  input rst_i,
  input clk_i,

  input write_i,
  input read_i,

  output empty_o,
  output full_o,

  //output data_valid_o,

  input [(DATA_WIDTH-1) : 0] data_i,
  output reg [(DATA_WIDTH-1) : 0] data_o

);

// need to "count" to number *including* depth
reg [$clog2(DATA_DEPTH + 1)-1:0] r_count;
reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0];
reg [$clog2(DATA_DEPTH)-1:0] r_read_addr;
reg [$clog2(DATA_DEPTH)-1:0] r_write_addr;

initial begin
  r_count = 0;
  r_read_addr = 0;
  r_write_addr = 0;
end

always @(posedge clk_i or negedge rst_i) begin
  if (!rst_i) begin
    r_count <= 0;
    r_read_addr <= 0;
    r_write_addr <= 0;
  end else if (write_i && read_i) begin
    r_count <= r_count + 1;
    r_datastore[r_write_addr] <= data_i;
    // nothing to do
  end else if (write_i && !full_o) begin
    r_count <= r_count + 1;
    r_datastore[r_write_addr] <= data_i;
  end else if (read_i && !empty_o) begin
    r_count <= r_count - 1;
  end

  if (!rst_i) begin
  end else if (write_i && !full_o) begin
    // the_verilator wrongly (???) assumes DATA_DEPTH-1 requires 1 more bit than it does?
    if ({1'b0, r_write_addr} < (DATA_DEPTH - 1))
      r_write_addr <= r_write_addr + 1;
    else
      r_write_addr <= 0;
  end else if (read_i && !empty_o) begin
    // the_verilator wrongly (???) assumes DATA_DEPTH-1 requires 1 more bit than it does?
    if ({1'b0, r_read_addr} < (DATA_DEPTH - 1))
      r_read_addr <= r_read_addr + 1;
    else
      r_read_addr <= 0;
  end
end

assign empty_o = r_count == 0;
assign full_o = r_count == DATA_DEPTH;

endmodule