module fifo #(
  parameter DATA_WIDTH = 8,
  parameter DATA_DEPTH = 1024
) (
  input rst_i,
  input clk_i,

  input write_i,
  input read_i,

  output empty_o,
  output full_o,

  output data_valid_o,

  input [(DATA_WIDTH-1) : 0] data_i,
  output [(DATA_WIDTH-1) : 0] data_o

);

reg [$clog2(DATA_DEPTH):0] r_count;

initial begin
  r_count = 0;
end

always @(posedge clk_i or negedge rst_i) begin
  if (!rst_i) begin
    r_count <= 0;
  end else if (write_i && read_i) begin
    // nothing to do
  end else if (write_i && !full_o) begin
    r_count <= r_count + 1;
  end else if (read_i && !empty_o) begin
    r_count <= r_count - 1;
  end
end

assign empty_o = r_count == 0;
assign full_o = r_count >= DATA_DEPTH - 1;


endmodule