`timescale 1us/1ns

module fizzbuzz_tb (
);


reg [7:0] number = 0;
reg[2:0] fftst;
wire [7:0] num_out;
reg clk_i = 0;

fizzbuzz uut(
  .clk_i(clk_i),
  .num_i(number),
  .num_o(num_out),
  .fizz_o(),
  .buzz_o(),
  .fizzbuzz_o(),
  // I still don't 100% get non-blocking assignments
  .ff_test_o(fftst)
);

initial begin
  $dumpfile("fizzbuzz.lxt2"); $dumpvars();

end

always #10 begin
  number <= number + 1;
  clk_i <= ~clk_i;
  if (number == 3) assert(num_out == 0);
  if (number == 5) assert(num_out == 0);
  if (number == 15) assert(num_out == 0);
end

initial begin
  #2570
  $finish();
end

endmodule