module fizzbuzz (
  input clk_i,
  input [7:0] num_i,
  output [7:0] num_o,
  output fizz_o,
  output buzz_o,
  output fizzbuzz_o,
  output reg[2:0] ff_test_o
);

wire is_fizz, is_buzz;
assign is_fizz = num_i % 3 == 0;
assign is_buzz = num_i % 5 == 0;

assign fizz_o = is_fizz && !is_buzz;
assign buzz_o = !is_fizz && is_buzz;
assign fizzbuzz_o = is_fizz && is_buzz;
assign num_o = (is_fizz || is_buzz) ? 0 : num_i;


initial begin
  ff_test_o = 0;
end

always @(posedge clk_i ) begin
  if (num_i == 11)
    ff_test_o <= 1;
  else if (num_i == 13)
    ff_test_o <= 2;
  else if (num_i == 17)
    ff_test_o <= 3;
  else if (num_i == 23)
    ff_test_o <= 4;
  
end

endmodule