module fizzbuzz (
  input [7:0] num_i,
  output [7:0] num_o,
  output fizz_o,
  output buzz_o,
  output fizzbuzz_o
);

wire is_fizz, is_buzz;
assign is_fizz = num_i % 3 == 0;
assign is_buzz = num_i % 5 == 0;

assign fizz_o = is_fizz && !is_buzz;
assign buzz_o = !is_fizz && is_buzz;
assign fizzbuzz_o = is_fizz && is_buzz;
assign num_o = (is_fizz || is_buzz) ? 0 : num_i;

endmodule