`include "clkdiv.v"

module led (
    input clk,              // clk input
    input rst_i,              // reset input
    output reg [5:0] led    // 6 LEDS pin
);

reg myclk;

clkdiv bla(
  .rst_i(rst_i),
  .clk(clk),
  .o_divclk(myclk)
);

always @(posedge myclk or negedge rst_i) begin
    if (!rst_i)
        led <= 6'b111111;
    else
//    else if (counter == 24'd1349_9999)       // 0.5s delay
        led[5:0] <= led[5:0] - 1;
//    else
//        led <= led;
end


endmodule