`timescale 1us/1us

module my_mem #(
  parameter DATA_WIDTH = 8,
  parameter DATA_DEPTH = 1024
) (
  input clk_i,

  input write_en_i,
  input read_en_i,

  input [$clog2(DATA_DEPTH)-1:0] r_read_addr,
  input [$clog2(DATA_DEPTH)-1:0] r_write_addr,

  input [(DATA_WIDTH-1) : 0] data_i,
  output reg [(DATA_WIDTH-1) : 0] data_o
);

reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0];

always @(posedge clk_i) begin
  if (write_en_i) begin
    r_datastore[r_write_addr] <= data_i;
  end

  if (read_en_i) begin
    data_o <= r_datastore[r_read_addr];
  end
end

endmodule