// LLM generated, because I'm too lazy to do this manually

`timescale 1us/1ns

module my_mem_tb();

  localparam DATA_WIDTH = 8;
  localparam DATA_DEPTH = 16;
  localparam ADDR_WIDTH = $clog2(DATA_DEPTH);

  // DUT signals
  logic clk;
  logic write_en_i;
  logic read_en_i;
  logic [ADDR_WIDTH-1:0] r_read_addr;
  logic [ADDR_WIDTH-1:0] r_write_addr;
  logic [DATA_WIDTH-1:0] data_i;
  logic [DATA_WIDTH-1:0] data_o;

  // Instantiate DUT
  my_mem #(
    .DATA_WIDTH(DATA_WIDTH),
    .DATA_DEPTH(DATA_DEPTH)
  ) dut (
    .clk_i(clk),
    .write_en_i(write_en_i),
    .read_en_i(read_en_i),
    .r_read_addr(r_read_addr),
    .r_write_addr(r_write_addr),
    .data_i(data_i),
    .data_o(data_o)
  );

  string filename;
  initial begin
  `ifdef DUMP_FILE_NAME
    filename=`DUMP_FILE_NAME;
  `else
    filename="my_mem.lxt2";
  `endif
    $dumpfile(filename); $dumpvars();
  end

  // Clock generator
  always #10 clk = ~clk;

  // Test sequence
  initial begin
    clk = 0;
    write_en_i = 0;
    read_en_i  = 0;
    r_read_addr  = '0;
    r_write_addr = '0;
    data_i = '0;

    repeat (3) @(negedge clk);

    // -------------------------
    // Write some values
    // -------------------------
    @(negedge clk);
    write_en_i   = 1;
    r_write_addr = 10;
    data_i       = 8'hA5;

    @(negedge clk);
    r_write_addr = 11;
    data_i       = 8'h3C;

    @(negedge clk);
    write_en_i = 0;

    // -------------------------
    // Read back values
    // -------------------------

    @(negedge clk);
    read_en_i   = 1;
    r_read_addr = 10;

    @(negedge clk);
    assert (data_o == 8'hA5)
    else $error("ASSERTION FAILED: addr 10 expected 0xA5, got 0x%02h", data_o);

    @(negedge clk);
    r_read_addr = 11;

    @(negedge clk);
    assert (data_o == 8'h3C)
    else $error("ASSERTION FAILED: addr 11 expected 0x3C, got 0x%02h", data_o);

    @(negedge clk);
    read_en_i = 0;

    repeat (3) @(negedge clk);
    $finish;
  end

endmodule