`timescale 1us/1us

`include "nandgame_types.v"

module alu_tb;

logic [15:0] tst_in1;
logic [15:0] tst_in2;
logic [1:0] tst_opcode;
logic [15:0] tst_result;
logic tst_is_arith_nlogic, tst_zero_x, tst_swap_operands;

alu uut (
  .X_in(tst_in1),
  .Y_in(tst_in2),
  .opcode_in(tst_opcode),
  .result_out(tst_result),
  .u_arith_nlogic_in(tst_is_arith_nlogic),
  .zx_in(tst_zero_x),
  .sw_in(tst_swap_operands)
);

string filename;
initial begin
`ifdef DUMP_FILE_NAME
  filename=`DUMP_FILE_NAME;
`else
  filename="alu.lxt2";
`endif
  $dumpfile(filename); $dumpvars();
end

initial begin
  tst_zero_x = 0;
  tst_swap_operands = 0;

  // Arith tests
  tst_is_arith_nlogic = 1;
  tst_in1 = 13;
  tst_in2 = 17;
  tst_opcode = ARITH_PLUS;
  #1
  assert(tst_result == 30)
  else $error("Expected: 30, got: %d", tst_result);
  #1
  tst_in1 = 12;
  tst_in2 = 4;
  tst_opcode = ARITH_MINUS;
  #1
  assert(tst_result == 8)
  else $error("Expected: 8, got: %d", tst_result);
  #1
  tst_in1 = 12;
  tst_in2 = 13;
  tst_opcode = ARITH_MINUS;
  #1
  assert(tst_result == 16'hffff)
  else $error("Expected: 16'hffff, got: %d", tst_result);
  #1
  tst_in1 = 13;
  tst_in2 = 17;
  tst_opcode = ARITH_INC;
  #1
  assert(tst_result == 14)
  else $error("Expected: 14, got: %d", tst_result);
  #1
  tst_in1 = 13;
  tst_in2 = 17;
  tst_opcode = ARITH_DEC;
  #1
  assert(tst_result == 12)
  else $error("Expected: 12, got: %d", tst_result);
  #1
  tst_in1 = 0;
  tst_in2 = 17;
  tst_opcode = ARITH_DEC;
  #1
  assert(tst_result == 16'hffff)
  else $error("Expected: 16'hffff, got: %d", tst_result);
  #1

  // logic tests
  tst_is_arith_nlogic  = 0;
  tst_in1 = 16'b1010;
  tst_in2 = 16'b1100;
  tst_opcode = LOGIC_AND;
  #1
  assert(tst_result == 16'b1000)
  else $error("Expected: 16'b1000, got: %d", tst_result);
  #1
  tst_in1 = 16'b1010;
  tst_in2 = 16'b1100;
  tst_opcode = LOGIC_OR;
  #1
  assert(tst_result == 16'b1110)
  else $error("Expected: 16'b1110, got: %d", tst_result);
  #1
  tst_in1 = 16'b1010;
  tst_in2 = 16'b1100;
  tst_opcode = LOGIC_XOR;
  #1
  assert(tst_result == 16'b0110)
  else $error("Expected: 16'b0110, got: %d", tst_result);
  #1
  tst_in1 = 16'b1010101010101010;
  tst_opcode = LOGIC_NEGT;
  #1
  assert(tst_result == 16'b0101010101010101)
  else $error("Expected: 16'b0101010101010101, got: %d", tst_result);
  #1

  // zero - tests
  tst_zero_x = 1;
  tst_swap_operands = 0;
  // back to logic
  tst_is_arith_nlogic = 0;
  tst_in1 = 2;
  tst_in2 = 4;
  tst_opcode = LOGIC_OR;
  #1
  assert(tst_result == 4)
  else $error("Expected 4, got %d", tst_result);
  #1

  // back to arith
  tst_is_arith_nlogic = 1;
  tst_in1 = 2;
  tst_in2 = 4;
  tst_opcode = ARITH_PLUS;
  #1
  assert(tst_result == 4)
  else $error("Expected 4, got %d", tst_result);
  #1

  // swap tests
  tst_zero_x = 0;
  tst_swap_operands = 1;
  tst_is_arith_nlogic = 1;
  tst_in1 = 2;
  tst_in2 = 3;
  tst_opcode = ARITH_MINUS;
  #1
  // 3 - 2
  assert(tst_result == 1)
  else $error("Expected 1, got %d", tst_result);

  // zero-swap
  tst_zero_x = 1;
  tst_swap_operands = 1;
  tst_is_arith_nlogic = 1;
  tst_in1 = 2;
  tst_in2 = 3;
  tst_opcode = ARITH_PLUS;
  #1
  // 2 + 0
  assert(tst_result == 2)
  else $error("Expected 2, got %d", tst_result);

  $finish();
end

endmodule