// nandgame "combined memory"
// contains registers A, D and *A result
// located in memory.

`timescale 1us/1us

`include "../my_mem.v"

`ifndef COMB_MEM
`define COMB_MEM

module comb_mem #(
  parameter DATA_WIDTH = 16
) (
    // store to A register
    input store_to_a_in,
    // store to D register
    input store_to_d_in,
    // store to address in memory pointed to by A (currently)
    input store_to_pa_in,

    // value to store
    input [(DATA_WIDTH-1):0] X_in,
    // output registers updated on falling edge
    input wire clk_in,

    // content of A register
    output reg [(DATA_WIDTH-1):0] reg_A_out,
    // content of D register
    output reg [(DATA_WIDTH-1):0] reg_D_out,
    // content memory pointed to by A register
    output reg [(DATA_WIDTH-1):0] reg_pA_out
);

wire inv_clk_int;
// my hw uses posedge, nandgame uses negedge.
assign inv_clk_int = ~clk_in;

my_mem #(
    .DATA_WIDTH(DATA_WIDTH),
    .DATA_DEPTH(65536)
) nand_memory (
    .clk_i(inv_clk_int),
    .write_en_i(store_to_pa_in),
    .read_en_i(1'b1),
    .r_read_addr(reg_A_out),
    .r_write_addr(reg_A_out),
    .data_o(reg_pA_out),
    .data_i(X_in)
);

initial begin
    reg_A_out = 0;
    reg_D_out = 0;
end

always @(negedge clk_in) begin
    if (store_to_a_in)
        reg_A_out <= X_in;

    if (store_to_d_in)
        reg_D_out <= X_in;
end

endmodule

`endif