`timescale 1us/1us

module comb_mem_tb;

reg clk_i;
logic wa, wd, wpa;
logic [15:0] o_a, o_d, o_pa;
logic [15:0] X;

comb_mem uut (
  .cl(clk_i),
  .a_i(wa),
  .d_i(wd),
  .pa_i(wpa),
  .A_o(o_a),
  .D_o(o_d),
  .pA_o(o_pa),
  .X(X)
);

string filename;
initial begin
`ifdef DUMP_FILE_NAME
  filename=`DUMP_FILE_NAME;
`else
  filename="comb_mem.lxt2";
`endif
  $dumpfile(filename);
  $dumpvars();
  clk_i = 0;
  wa = 0; wd = 0; wpa = 0;
  X = 16'h55;
end

always #10 clk_i = ~clk_i;

initial begin

  repeat(3) @(posedge clk_i);
  wa = 1;
  repeat(3) @(posedge clk_i);
  wa = 0;
  wd = 1;
  repeat(3) @(posedge clk_i);
  wd = 0;
  wpa = 1;
  X = 16'haa;
  repeat(3) @(posedge clk_i);

  $finish();
end

endmodule