`timescale 1us/1ns

module par_to_ser_tb (
);

reg clk_i;
reg rst_i;
reg data_valid_i;
reg [7:0] dat_i;
wire dat_o;

par_to_ser uut(
  .clk_i(clk_i),
  .rst_i(rst_i),
  .data_valid_i(data_valid_i),
  .dat_i(dat_i),
  .dat_o(dat_o)
);

initial begin
  $dumpfile("par_to_ser.lxt2"); $dumpvars();
  clk_i <= 0;
  rst_i <= 1'b1;
  data_valid_i <= 1'b0;

  #1
  rst_i <= 1'b0;
  #1
  rst_i <= 1'b1;
end

always #10 clk_i = ~clk_i;

initial begin
  #37

  for (integer i = 0; i < 255; i++) begin
    // clock data in
    dat_i <= i;
    data_valid_i <= 1'b1;

    // wait 1 cycle
    #20
    data_valid_i <= 1'b0;

    // let module do its work
    #200
    ;

  end

  $finish();
end

endmodule