`timescale 1us/1ns

module par_to_ser_tb (
);

reg clk_i;
reg rst_i;
reg do_send_i;
reg [7:0] dat_i;
wire dat_o;

par_to_ser uut(
  .clk_i(clk_i),
  .rst_i(rst_i),
  .do_send_i(do_send_i),
  .dat_i(dat_i),
  .dat_o(dat_o)
);

initial begin
  $dumpfile("par_to_ser.lxt2"); $dumpvars();
  clk_i <= 0;
  rst_i <= 1'b1;
  do_send_i <= 1'b0;

  #1
  rst_i <= 1'b0;
  #1
  rst_i <= 1'b1;
end

always #10 clk_i = ~clk_i;

initial begin
  #37
  dat_i <= 8'haa;
  #13
  do_send_i <= 1'b1;
  // wait 8 clock cycles?
  #80

  do_send_i <= 1'b0;

  #400
  $finish();
end

endmodule