// parallel to serial converter

module par_to_ser #(
  SHIFT_WIDTH = 8
) (
  input rst_i,
  input clk_i,
  input data_valid_i,
  input [(SHIFT_WIDTH-1):0] dat_i,
  output reg dat_o
);

// Learning: can't declate parameter here
// if I want to use it in the input/output list.
// parameter SHIFT_WIDTH = 8;

reg [7:0] send_data = 8'hff;
// want to count to number *including* width, add 1
reg [$clog2(SHIFT_WIDTH + 1) - 1:0] count = 0;

wire counting, sending;

// sending is one byte longer
assign sending = (count != 0) && (count <= SHIFT_WIDTH);
// yes, smaller than, the count *to* 8 still takes place
assign counting = (count != 0) && (count < SHIFT_WIDTH);

always @(posedge clk_i or negedge rst_i) begin
  if (!rst_i) begin
    dat_o <= 1'b1;
  end else if (data_valid_i && count == 0) begin
    dat_o <= dat_i[0];
  end else if (sending) begin
    dat_o <= send_data[0];
  end
end

always @(posedge clk_i or negedge rst_i) begin
  if (!rst_i) begin
    send_data <= 8'hff;
  end else if (data_valid_i && count == 0) begin
    send_data <= {1'b1, dat_i[7:1]};
  end else if (sending) begin
    // arbitrary decision: register is filled with a 1
    send_data <= {1'b1, send_data[7:1]};
  end
end

always @(posedge clk_i or negedge rst_i) begin
  if (!rst_i) begin
    count <= 0;
  end else if (data_valid_i && count == 0) begin
    count <= 1;
  end else if (counting) begin
    count <= count + 1;
  end else begin
    count <= 0;
  end
end

endmodule