// converts back and forth
// parallel > serial > parallel

`timescale 1us/1us

module par_to_ser_to_par_tb (
);

logic clk_i;
logic rst_i;
logic data_valid_i;
logic [7:0] dat_i;

logic dat_o;
logic [7:0] dat_o2;
logic send_valid;

par_to_ser uut (
  .clk_i(clk_i),
  .rst_i(rst_i),
  .data_valid_i(data_valid_i),
  .dat_i(dat_i),
  .dat_o(dat_o),
  .dat_valid_o(send_valid)
);

ser_to_par uut2 (
  .clk_i(clk_i),
  .rst_i(rst_i),

  .dat_valid_i(send_valid),
  .dat_i(dat_o),

  .dat_o(dat_o2),
  .dat_valid_o()
);

string filename;
initial begin
`ifdef DUMP_FILE_NAME
  filename=`DUMP_FILE_NAME;
`else
  filename="par_to_ser_to_par.lxt2";
`endif
  $dumpfile(filename); $dumpvars();
  clk_i = 0;
  rst_i = 1'b1;
  data_valid_i = 1'b0;

  #1
  rst_i = 1'b0;
  #1
  rst_i = 1'b1;
end

always #10 clk_i = ~clk_i;

initial begin
  #13;
  @(negedge clk_i);

  for (integer i = 0; i < 255; i++) begin
    // clock data in
    dat_i = i;
    data_valid_i = 1'b1;

    // wait 1 cycle
    @(negedge clk_i);
    data_valid_i = 1'b0;

    // let module do its work
    repeat(10) @(negedge clk_i);
  
    assert(i == dat_o2)
    else $error("Expected output to be h%x, but was h%x", i, dat_o2);

  end

  $finish();
end

endmodule