`timescale 1us/1ns

module ser_to_par_tb (
);

reg clk_i;
reg rst_i;
reg dat_i;
wire [7:0] dat_o;

ser_to_par uut(
  .clk_i(clk_i),
  .rst_i(rst_i),
  .dat_i(dat_i),
  .dat_o(dat_o)
);

initial begin
  $dumpfile("ser_to_par.lxt2"); $dumpvars();
  clk_i <= 0;
  rst_i <= 1'b1;
  dat_i <= 1'b1;
  #1
  rst_i <= 0;
  #1
  rst_i <= 1;
end

always #10 clk_i = ~clk_i;

initial begin
  #37

  // start data
  dat_i <= 1'b0;
  #20

  // - 1 clk cycle, 1 bit later:
  dat_i <= 1'b1;

  #140
  // - 7 clk cycle, 7 bits later:
  assert (dat_o == 8'hfe)

  #20
  $finish();
end

endmodule