// serial to parallel converter
// Learning:
// I don't like this.
// I think I need a signal / way to say "I'm finished"?
// or generally, an enable pin.
//

module ser_to_par #(
  parameter SHIFT_WIDTH = 8
) (
  input rst_i,
  input clk_i,

  input dat_valid_i,
  input dat_i,

  output reg[(SHIFT_WIDTH - 1):0] dat_o,
  // ???
  output dat_valid_o
);

reg [$clog2(SHIFT_WIDTH) - 1 : 0] count = {$clog2(SHIFT_WIDTH){1'b0}};

always @(posedge clk_i or negedge rst_i) begin
  if (!rst_i) begin
    dat_o <= 8'b0;
  end else if(dat_valid_i) begin
    // shift into highest bit first, so it is subsequently shifted down
    dat_o[SHIFT_WIDTH - 1] <= dat_i;
    dat_o[(SHIFT_WIDTH - 2):0] <= dat_o[(SHIFT_WIDTH - 1):1];
    count <= count + 1;
  end
end

assign dat_valid_o = count == 0;

endmodule