`timescale 1us/1ns

module template_tb (
);

reg clk_i;
reg rst_i;

template uut(
  .clk_i(clk_i),
  .rst_i(rst_i)
);

initial begin
  clk_i <= 0;
  rst_i <= 1'b1;

  $dumpfile("template.lxt2"); $dumpvars();
end

always #10 clk_i = ~clk_i;

initial begin
  #100
  $finish();
end

endmodule