// try to figure out how iverilog samples edges
`timescale 1us/1ns

module template_tb (
);

reg clk_i;
reg data_i;
wire data_o;

tst_delay uut(
  .clk_i(clk_i),
  .data_i(data_i),
  .data_o(data_o)
);

initial begin
  $dumpfile("tst_delay.lxt2"); $dumpvars();
  clk_i = 0;
  data_i = 0;
end

always #10 clk_i = ~clk_i;

initial begin
  #9
  data_i = 1;
  #2
  data_i = 0;
  // note the <= assignment
  #19
  data_i <= 1;
  #1
  data_i = 0;
  // note the = assignment
  #19
  data_i = 1;
  #1
  data_i = 0;
  #40
  $finish();
end

endmodule