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Learnings:
- Anything that needs to "store" a state must be a reg?
=> wire's can't be assigned in always blocks, yosys complains
- regs must not lead to wires? (unsure where I read that)
- https://blog.waynejohnson.net/doku.php/verilog_wire_and_reg
-> wires of an outer module can be connecting to an inner module.
-> reg can be input to an inner module
-> regs can't be outputs
- Clock on the tang9k is 27 MHz
Questions:
- Why do so many examples use always @(posedge clk or nededge rst).
i.e., why is the clk always included?
- "async reset" - asynchronous events might be missed, and they
don't work well with clocked registers.
- Does yosys and other tools "automatically" determine the
"perfect" wire/register (bus) width if I just specify e.g.
wire BLA = 1374;
?
- The book tasked me with writing a serial-to-parallel and parallel-to-serial converter.
But I think I wrote it "wrong"?
If I used this in the real world, and chained both components together,
things would go wrong. as the output is flipped at the rising clock
edge - violating timings and leading to unpredictable behavior?
Or not?
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