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// represents the Ben Eater 8bit computer - ALU
`timescale 1us/1us
`include "eater_types.sv"
module eater_alu (
input wire clk_in,
input wire en_output_in,
input wire subtract_n_add_in,
input wire [7:0] A_in,
input wire [7:0] B_in,
output wire [7:0] bus_out,
output wire AluFlags flags_out
);
wire [8:0] full_result /* verilator public */;
wire [7:0] result /* verilator public */;
assign full_result = subtract_n_add_in ? (A_in - B_in) : (A_in + B_in);
assign result = full_result[7:0];
// wire [7:0] xormask = {8{subtract_n_add_in}};
// wire [7:0] B_neg_if = B_in ^ xormask;
// wire [7:0] result2 = A_in + B_neg_if + subtract_n_add_in;
zbuffer buffer (
.data_in(result),
.en_output_in(en_output_in),
.data_out(bus_out)
);
assign flags_out.Zero = (result == 0);
assign flags_out.Carry = full_result[8] == 1;
assign flags_out.reserved = 'b0;
endmodule
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