eater_cpu/eater_alu_tb.sv


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`timescale 1us/1us

module eater_alu_tb;

logic sub_n_add;
logic [7:0] A, B, out;

eater_alu uut(
    .clk_in(1'b0),
    .subtract_n_add_in(sub_n_add),
    .A_in(A),
    .B_in(B),
    .en_output_in(1'b1),
    .bus_out(out)
);

initial begin
    $dumpfile("eater_alu.vvp");
    $dumpvars();

    sub_n_add = 0;
    A = 10;
    B = 5;
    #1
    assert(out == 15)
    else $error("Exptected 15, got %d", out);
    #1;
    sub_n_add = 1;
    #1
    assert(out == 5)
    else $error("Exptected 15, got %d", out);
    #1;
    $finish();
end
    
endmodule