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// represents the Ben Eater 8bit computer
`timescale 1us/1us
module eater_computer(
output [7:0] debug_bus
);
logic clk_in;
/* verilator public_on */
tri [7:0] bus;
logic A_to_bus, bus_to_A,
B_to_bus, bus_to_B,
INS_to_bus, bus_to_INS
;
assign debug_bus = bus;
/* verilator public_off */
eater_register A (
.clk_i(clk_in),
.en_store_i(bus_to_A),
.en_output_i(A_to_bus),
.data_i(bus),
.data_o(bus)
);
eater_register B (
.clk_i(clk_in),
.en_store_i(bus_to_B),
.en_output_i(B_to_bus),
.data_i(bus),
.data_o(bus)
);
tri [7:0] ins_bus_out;
assign bus[3:0] = ins_bus_out[3:0];
eater_register INS (
.clk_i(clk_in),
.en_store_i(bus_to_INS),
.en_output_i(INS_to_bus),
.data_i(bus),
.data_o(ins_bus_out)
);
`ifdef VERILATOR
initial begin
$dumpfile("simpc.vvp");
$dumpvars();
A_to_bus = 0;
B_to_bus = 0;
bus_to_A = 0;
bus_to_B = 0;
clk_in = 0;
end
always #2 clk_in = ~clk_in;
initial begin
#10
$finish();
end
`endif
endmodule
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