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// represents the Ben Eater 8bit computer
`timescale 1us/1us
module eater_computer(
input clk_in,
output [7:0] debug_bus
);
/* verilator public_on */
tri [7:0] bus, A_out, B_out;
logic A_to_bus, bus_to_A,
B_to_bus, bus_to_B,
INS_to_bus, bus_to_INS,
ALU_to_bus
;
assign debug_bus = bus;
/* verilator public_off */
eater_register A (
.clk_in(clk_in),
.en_store_in(bus_to_A),
.en_output_in(A_to_bus),
.data_in(bus),
.bus_out(bus),
.always_out(A_out)
// .data(bus)
);
eater_register B (
.clk_in(clk_in),
.en_store_in(bus_to_B),
.en_output_in(B_to_bus),
.data_in(bus),
.bus_out(bus),
.always_out(B_out)
// .data(bus)
);
tri [7:0] ins_bus_out;
assign bus[3:0] = ins_bus_out[3:0];
eater_register INS (
.clk_in(clk_in),
.en_store_in(bus_to_INS),
.en_output_in(INS_to_bus),
.data_in(bus),
.bus_out(ins_bus_out),
.always_out()
// .data(ins_bus_out)
);
eater_alu alu (
.clk_in(clk_in),
.en_output_in(ALU_to_bus),
.A_in(A_out),
.B_in(B_out),
.subtract_n_add_in(1'b0),
.bus_out(bus)
);
endmodule
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