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// represents the Ben Eater 8bit computer
`timescale 1us/1us
module eater_computer_tb;
logic clk_in;
eater_computer uut (
.debug_bus(),
.clk_in(clk_in)
);
logic [7:0] debug_value;
logic debug_enable;
bus_writer debugger (
.in_value(debug_value),
.in_write_to_output(debug_enable),
.out_value(uut.bus)
);
initial begin
$dumpfile("simpc.vvp");
$dumpvars();
uut.A_to_bus = 0;
uut.B_to_bus = 0;
uut.INS_to_bus = 0;
uut.ALU_to_bus = 0;
uut.bus_to_A = 0;
uut.bus_to_B = 0;
uut.bus_to_INS = 0;
clk_in = 0;
debug_enable = 0;
debug_value = 'z;
end
always #2 clk_in = ~clk_in;
initial begin
@(negedge clk_in);
debug_value = 'haa;
debug_enable = 1;
uut.bus_to_A = 1;
@(negedge clk_in);
uut.bus_to_A = 0;
debug_value = 'hbb;
uut.bus_to_B = 1;
@(negedge clk_in);
uut.bus_to_B = 0;
debug_value = 'hcc;
uut.bus_to_INS = 1;
@(negedge clk_in);
debug_enable = 0;
debug_value = 'z;
uut.bus_to_INS = 0;
@(negedge clk_in);
uut.A_to_bus = 1;
@(negedge clk_in);
assert (uut.bus == 'haa)
else $error("Expected 0xaa, got 0x%02x on bus", uut.bus);
uut.A_to_bus = 0;
@(negedge clk_in);
uut.ALU_to_bus = 1;
@(negedge clk_in);
assert (uut.bus == 8'('haa + 'hbb))
else $error("Expected 0x%02x, got 0x%02x on bus", 8'('haa + 'hbb), uut.bus);
#10
$finish();
end
endmodule
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