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// represents the Ben Eater 8bit computer
`timescale 1us/1us
module eater_computer_tb;
logic clk_in;
eater_computer uut (
.debug_bus(),
.clk_in(clk_in)
);
logic [7:0] debug_value;
logic debug_enable;
zbuffer debugger (
.data_in(debug_value),
.en_output_in(debug_enable),
.data_out(uut.bus)
);
initial begin
$dumpfile("simpc.vvp");
$dumpvars();
uut.flags.A_out = 0;
uut.flags.B_out = 0;
uut.flags.INS_out = 0;
uut.flags.ALU_out = 0;
uut.flags.RAM_out = 0;
uut.flags.PC_out = 0;
uut.flags.PC_count = 0;
uut.flags.A_in = 0;
uut.flags.B_in = 0;
uut.flags.INS_in = 0;
uut.flags.RAM_in = 0;
uut.flags.PC_in = 0;
uut.flags.MAR_in = 0;
clk_in = 0;
debug_enable = 0;
debug_value = 'z;
end
always #2 clk_in = ~clk_in;
initial begin
@(negedge clk_in);
debug_enable = 1;
@(negedge clk_in);
debug_value = 'h00;
uut.flags.MAR_in = 1;
@(negedge clk_in);
uut.flags.MAR_in = 0;
debug_value = 'h04;
uut.flags.PC_in = 1;
@(negedge clk_in);
uut.flags.PC_in = 0;
debug_value = 'haa;
uut.flags.A_in = 1;
@(negedge clk_in);
uut.flags.A_in = 0;
debug_value = 'hbb;
uut.flags.B_in = 1;
@(negedge clk_in);
uut.flags.B_in = 0;
debug_value = 'hcc;
uut.flags.INS_in = 1;
@(negedge clk_in);
uut.flags.INS_in = 0;
debug_value = 'hdd;
uut.flags.RAM_in = 1;
@(negedge clk_in);
uut.flags.RAM_in = 0;
@(negedge clk_in);
debug_enable = 0;
debug_value = 'z;
@(negedge clk_in);
uut.flags.A_out = 1;
@(negedge clk_in);
assert (uut.bus == 'haa)
else $error("Expected 0xaa (from REG A), got 0x%02x on bus", uut.bus);
uut.flags.A_out = 0;
uut.flags.B_out = 1;
@(negedge clk_in);
assert (uut.bus == 'hbb)
else $error("Expected 0xbb (from REG B), got 0x%02x on bus", uut.bus);
uut.flags.B_out = 0;
uut.flags.INS_out = 1;
@(negedge clk_in);
assert (uut.bus == 'h0c)
else $error("Expected 0x0c (from INS), got 0x%02x on bus", uut.bus);
// ERROR: TODO: should I expect 'zc or '0c ?
uut.flags.INS_out = 0;
@(negedge clk_in);
uut.flags.ALU_out = 1;
@(negedge clk_in);
assert (uut.bus == 8'('haa + 'hbb))
else $error("Expected 0x%02x (from ALU), got 0x%02x on bus", 8'('haa + 'hbb), uut.bus);
uut.flags.ALU_out = 0;
uut.flags.PC_out = 1;
@(negedge clk_in);
assert (uut.bus == 'h04)
else $error("Expected 0x04 (from PC), got 0x%02x on bus", uut.bus);
uut.flags.PC_out = 0;
uut.flags.RAM_out = 1;
@(negedge clk_in);
assert (uut.bus == 'hdd)
else $error("Expected 0xdd (from RAM), got 0x%02x on bus", uut.bus);
uut.flags.RAM_out = 0;
@(negedge clk_in);
debug_enable = 1;
debug_value = 'h01;
uut.flags.MAR_in = 1;
@(negedge clk_in);
debug_enable = 0;
debug_value = 'bz;
uut.flags.MAR_in = 0;
uut.flags.RAM_out = 1;
@(negedge clk_in);
$info("Got 0x%02x from RAM", uut.bus);
assert (uut.bus !== 'hdd)
else $error("Did NOT expectd 0xdd (from RAM)");
#10
$finish();
end
endmodule
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